This invention relates to a bipolar transistor and, more particularly, to a lateral bipolar semiconductor device made by using semiconductor thin films like SOI (silicon on insulator) layer on an insulating substrate.
Bipolar transistor (hereinafter called xe2x80x9cBJTxe2x80x9d) made by using SOI layers are expected to be operative at a higher speed because of the lower floating capacitance as compared with transistors made on bulk silicon substrates. One of literatures disclosing such BJT is, for example, IEEE EDL-8, No. 3, p. 104, 1987 by J. C. Sturm, et al.
FIG. 49 is a schematic cross-sectional view showing construction of BJT. BJT shown here is formed on an insulating film 2 stacked on a silicon substrate 1. That is, made on the insulating film 2 are an n+-type collector region 67, p-type intrinsic base region 63 and n+-type emitter region 68 in a close alignment in this order. Made on the intrinsic base region 63 in self alignment is a p+-type external base region 632 for ensuring contact with an electrode.
A manufacturing method of this structure is summarized below. First made on the insulating film 2 is an initial silicon layer having a thickness approximately reaching the surface of a p+-type layer 632, and an impurity is doped into the entirety to the impurity concentration of the intrinsic base region 63. Then, its surface is doped into a p+-type, and a thick insulating film is made in the region for the base region. Using this film as a mask, regions for the emitter and the collector are etched until removing the p+-type layer. Still using the thick insulating film as a mask, an n-type impurity is doped into the emitter and collector regions by ion implantation.
In the structure shown in FIG. 49, even if the base contact is made on the external base region 632 at one end of the element located in a vertical direction relative to the drawing sheet, electric bias from the contact to the intrinsic base region 63 results in being first transferred through the external base region 632 having a relatively low resistance, and then being supplied from an upper direction to a lower direction. Therefore, by enlarging the intrinsic base region 63 and the external base region 632 in width and by elongating the device along a direction vertical to the drawing sheet, the cross-sectional area vertical to the flow direction of the base current in the intrinsic base region and the external base region can be increased, and the base resistance can be decreased. The decrease of the base resistance leads to improvement of noise figure (NF) and maximum oscillation frequency (fmax) which are important performance indices for use of BJT as an analog element, and BJT having low-noise high fmax characteristics could be expected.
However, for use with high frequencies on the order of gigaherz, another performance index, the cut-off frequency (fT), must be improved. Actually, as shown in the following equation, the value of fT is closely related with NF and fmax, and high fT is indispensable also for good NF and fmax.             f      max        =                            f          T                          8          ⁢                      xe2x80x83                    ⁢          π          ⁢                      xe2x80x83                    ⁢                      R            B                    ⁢                      C            jc                                          N      F        =          1      +                                    q            ⁢                          xe2x80x83                        ⁢                          I              c                        ⁢                          R              B                                            k            ⁢                          xe2x80x83                        ⁢            T                          ⁢                                            (                              f                                  f                  T                                            )                        2                    ⁡                      [                          1              +                                                1                  +                                                                                    2                        ⁢                        k                        ⁢                                                  xe2x80x83                                                ⁢                        T                                                                    q                        ⁢                                                  xe2x80x83                                                ⁢                                                  I                          c                                                ⁢                                                  R                          B                                                                                      ⁢                                                                  (                                                                              f                            T                                                    f                                                )                                            2                                                                                            ]                              
where RB is the base resistance, Cjc is the capacitance between the base and the collector, q is the elementary charge Ic is the collector current, T is the absolute temperature, k is the Boltzmann constant, f is the frequency.
Therefore, in order to obtain high fT by reducing the carrier transit time in the base region, the width of the intrinsic base region 63 (distance from the emitter-side end to the collector-side end) must be reduced as small as 0.1 xcexcm or less.
This width cannot be sufficiently reduced due to dimensional limitation of lithography process. Even if it could be reduced, since it compels the overlying p+-type region to be narrowed, the base resistance of the external base region 632 increases, and sufficient NF and fmax could not be obtained.
On the other hand, as a literature disclosing a structure for supplying a base bias from an upper portion, there is a report in IEDM Tech. Dig. p. 663 (1991) by G. G. Shahidi, et al.
FIG. 50 is a cross-sectional view schematically showing BJT using the structure. A feature of this BJT lies in using p-type polycrystalline silicon (polysilicon) 163 for extension of the electrode from the base p-type region 63 toward the upper portion, and connecting it to low-resistance p+-type polysilicon 632. This p+-type polysilicon 632 is separated from the nxe2x88x92-type collector region by the insulating layer 169 and insulating side walls 168.
In this structure, since the intrinsic base and the external base are made independently to permit the external base to be made with a sufficient width even when the intrinsic base is narrowed, there is a possibility of overcoming the problem involved in the structure shown in FIG. 49.
In the structure of FIG. 50, however, since the lead-out portion 163 connecting the intrinsic base and the external base is made of a different material of polycrystalline silicon and so on, for example, it results in having contact resistance between the intrinsic base and the lead-out layer and between the lead-out layer and the external base respectively. Furthermore, the lead-out portion is made of polycrystalline silicon with a higher specific resistance than single crystalline silicon with the same impurity concentration. Therefore, actual base resistance increases significantly. In order to decrease the base resistance, there is the need for some additional measures, such as further increasing the length in the direction vertical to the drawing sheet, connecting a plurality of BJTs in parallel, for example, and its results in increasing the area each element occupies and increasing power consumption.
At the contact between the intrinsic base and the lead-out portion, the device property is liable to deteriorate due to turbulence in impurity profile. More specifically, if the impurity concentration in the lead-out is increased higher than that of the intrinsic base for the purpose of reducing the contact resistances and the resistance of the lead-out portion itself, impurities diffuse from the high-concentrated lead-out portion to the intrinsic base, and invites an increase in base concentration near the interface and an increase in the base width. As a result, current gain factor (hFE) and fT may decrease, and the junction with the high-concentrated emitter may deteriorate to permit tunneling junction leakage. In contrast, when the impurity concentration in the lead-out portion is lower than that of the intrinsic base, the base resistance increases, and impurities in the single-crystal silicon are rather absorbed out along the interface. Therefore, punch-through is liable to occur. Furthermore, since the depletion region extending from the emitter and collector to the base crosses over the lead-out portion along the contact interface, it may invites some additional problems, such as sudden increase in junction leakage, deterioration of the withstanding voltage, and so on.
To prevent these problems, it is necessary to set the width of the intrinsic base wider than that of the lead-out portion as illustrated in the drawing, and this inevitably invites a decrease of fT. In contrast, if the intrinsic base is narrowed, the lead-out portion must be more narrowed, and it results in increasing the base lead-out resistance. Therefore, it has been very difficult to improve the total performance.
There is a possibility of overcoming some of the above-indicated problems by making the base lead-out portion as a single crystal silicon layer by selective epitaxial growth instead of polycrystalline silicon. In this case, however, there will remain the same problems as those with polysilicon, because crystal irregularities are inevitably produced especially at peripheral edges of the epitaxial film. Moreover, influences derived from changes in structure for using an epitaxial layer and thermal process for its growth, use of an epitaxial growth technique, and so on, invite an increase of the manufacturing cost.
As discussed above, any of conventional BJTs configured to extend the base upward involves the problems: namely, upon reducing the width of the intrinsic base, difficulty in lithographic processing, increase of the base resistance therewith, deterioration of property at the lead out portion of polycrystalline silicon, for example, and a satisfactory high property could not be obtained.
The present invention has been made taking account of those problems. It is therefore an object of the invention to provide a semiconductor device as a bipolar transistor capable to reduce the width of the intrinsic base width without increasing the base lead-out resistance to obtain a remarkably good high-frequency property.
According to the invention, there is provided a bipolar transistor comprising:
an insulating layer having a major surface;
an island of single crystal semiconductor material selectively formed on said major surface of the insulating layer, said island including a collector region of a first conduction type and an intrinsic base region of a second conduction type located adjacent to said collector region; and
an emitter region of the first conduction type located adjacent to said intrinsic base region,
said island further including an external base region of the second conduction type located on said intrinsic base region and having a higher impurity concentration than said intrinsic base region.
According to the invention, there is also provided a bipolar transistor comprising:
an insulating layer having a major surface;
an island of single crystal semiconductor material selectively formed on said major surface of the insulating layer, said island including a collector region of a first conduction type and an intrinsic base region of a second conduction type located adjacent to said collector region; and
an emitter region of the first conduction type located adjacent to said intrinsic base region,
said island further including a monolithic protrusion projecting vertically upward relative to said major surface of said insulating layer located on said intrinsic base region,
said monolithic protrusion including an external base region of the second conduction type located near the uppermost layer thereof and having a higher impurity concentration than said intrinsic base region,
said monolithic protrusion further including a base lead-out region of the second conduction type formed along a side surface thereof and connecting said intrinsic base region external base region.
According to the invention, there is also provided a bipolar transistor comprising:
an insulating layer having a major surface; and
an island of semiconductor material selectively formed on said major surface of the insulating layer, and including a first collector region of a first conduction type, an emitter region of the first conduction type, an intrinsic base region of a second conduction type interposed between said collector region and said emitter region, which are closely located on said major surface of said insulating layer,
said island of semiconductor material further including a monolithic protrusion which is obtained by first providing a portion for said collector region and said intrinsic base region in a semiconductor layer provided on said major surface of said insulating layer, and removing a selective part of said semiconductor layer to a certain thickness thereof excluding at least a portion for said collector region and at least a portion for said intrinsic base region,
said monolithic protrusion further including an external base region made by introducing an impurity of said second conduction type from its upper surface, and
said monolithic protrusion further including a base lead-out region of the second conduction type provided along a side surface thereof to connect said intrinsic base region with said external base region.
According to the invention, there is also provided a manufacturing method of a bipolar transistor including:
an insulating layer having a major surface; and
an island of semiconductor material selectively formed on said major surface of the insulating layer, and including a first collector region of a first conduction type, an emitter region of the first conduction type, and an intrinsic base region of a second conduction type interposed between said collector region and said emitter region, which are closely located on said major surface of said insulating layer, comprising:
a first step of making a portion for said collector region and said intrinsic base region in a semiconductor layer provided on said major surface of said insulating layer;
a second step of making a monolithic protrusion by removing a selective part of said semiconductor layer to a certain thickness thereof excluding at least a portion for said collector region and at least a portion for said intrinsic base region;
a third step of making a base lead-out region of the second conduction type provided along a side surface of said monolithic protrusion to connect said intrinsic base region with said external base region;
a fourth step of making an external base region of the second conduction type near the uppermost layer of said monolithic protrusion by introducing an impurity of the second conduction type from an upper surface of said monolithic protrusion;
Components of the transistor from the intrinsic base to the lead-out region further to the external base region may be made as a monolithic (single crystal silicon layer to enable direct application of a base) bias from the external base the intrinsic base to without a contact. Thus, the problems of increase in base resistance and irregularities in crystal structure and impurity concentration profile can be removed.
The width of the external base region, which runs parallel to a line running between said emitter region and said collector region, is preferably larger than width of said intrinsic base region, which runs parallel to a line running between said emitter region and said collector region, so that a sufficiently low base resistance can be maintained even when the intrinsic base width is reduced.
The protrusion may be configured so that its side surfaces the collector region side approximately coincide with the head end of a depletion region which will extend during operation of the semiconductor device from the intrinsic base region into the collector region. Thus, the parasitic junction capacitance between the external base region and the collector region is suppressed to improve high-frequency characteristics such as fT and fmax and reduce the power consumption.
The protrusion may be configured so that lower ends of its side surfaces approximately coincide with the head ends of a depletion region which will extend during operation of the semiconductor device from the external base region toward the insulating layer into the collector region. Thus, by reserving the path for the collector current while reducing the parasitic capacitance, the collector resistance is maintained low, and an increase of the collector current density is alleviated, to thereby prevent a decrease of fT caused by so-called Kirk effect.
The collector region preferably includes a first collector region located adjacent to the intrinsic base region and having a first impurity concentration, and an external collector region adjacent to the first collector region and having a second impurity concentration higher than the first impurty concentration, so that, when a depletion region extends from the external base region during operation of the semiconductor device, its head ends coincide with junctions between the first collector region and the external collector region. Thus, while the collector resistance is maintained low, the base expansion effect is suppressed, thereby to improve the high-frequency property and maintain a high withstanding voltage of base-collector junction.
In a more specific mode, the semiconductor device according to the invention includes an external base region of the second conduction type having an impurity concentration around 1E18 cmxe2x88x923 and a region adjacent to the external base region having an impurity concentration of the fist conduction type as high as approximately 1E17 cmxe2x88x923, and includes a region having an impurity concentration of the first conduction type as high as approximately 1E18 to 1E19 cmxe2x88x923 in a location of the collector region where the current density becomes high.
Alternatively, the semiconductor device according to the invention may include a region having an impurity concentration of the first conduction type lower than the impurity concentration of the collector region in a location nearer to the base region, so that an electric bias of the support substrate be applied to induce majority carriers of the first conduction type in the collector region.
Furthermore, the semiconductor device according to the invention may include a buffer layer of polycrystalline silicon, for example, stacked on the protrusion to introduce impurities of the second conduction type through the buffer layer and thereby form the external base region. Thus, an impurity profile not extending so far into the silicon layer and having a steep gradient can be realized, and a high-concentrated, low-resistance external base region can be obtained while maintaining the collector region even when the silicon layer is initially thin.
The invention having the above-explained modes of use promises the effects explained below.
According to the invention, the p-type intrinsic base region and the nxe2x88x92-type collector region forming the xe2x80x9ctransverse arm portionsxe2x80x9d are configured to project upward from the substrate surface to form a protrusion, and the width P of the protrusion is wider than the width W of the intrinsic base region. Therefore, an excellent high-frequency property can be realized by reducing the base resistance while reducing the base width W.
Additionally, according to the invention, by making a buffer layer containing a p-type impurity on the protrusion and making the p+-type external base region by diffusion from the buffer layer, a shallow and very steep profile can be made with no tail-draggling in the SOI silicon layer, and the lead-out length of the external base region upward from the intrinsic base region can be shortened. Accordingly, the base resistance is remarkably reduced, the collector region is reliably reserved even when the SOI layer is reduced in thickness, and increase in collector resistance and occurrence of Kirk effect can be prevented.
Moreover, according to the invention, by configuring the protrusion so that its collector-side side surface approximately coincide with the head end of a deletion layer which will extend from the intrinsic base region to the collector region, parasitic capacitance between the base and collector can be minimized.
Furthermore, according to the invention, by making the effective distance of the current path between the p+-type region and the external collector region longer than the current path between the intrinsic base region and the external collector region to prevent degradation of breakdown voltage caused by the current path between the p+-type region and the external collector region, BJT excellent in high-frequency property can be realized, in which the base resistance is decreased without inviting degradation of the resistance voltage between the base and the collector.
According to the invention, by appropriately adjusting the configuration of the protrusion relative to the head end of the depletion region which extends from the external base region to the collector region during operation of BJT, the problem of the depletion region extending too far and blocking the path for the collector current is removed, to thereby reliably reserve the path of the collector current and prevent increase of the element resistance.
Further, according to the invention, by appropriately making a low-concentrated region in the collector region, it is possible to reduce the collector resistance without degrading the breakdown voltage of the collector and to prevent the base expansion effect. Thus, wider ranges of operation voltage and operation current are ensured, and high-frequency property is remarkably improved.
Moreover, according to the invention, when a so-called Corbino-type flat pattern is employed, no p-n junction is formed on the processed end surfaces of the element region. Therefore, breakdown voltage of the junction is improved, and leakage at the junction is suppressed. In contrast, by maintaining the processed end surfaces of the element region damaged, these portions can be used as a gettering site of contaminants like heavy metals, and the production yield of elements and their reliability can be improved.
As summarized above, the invention provides a semiconductor device having a good frequency property, high yield and high reliability while maintaining the base resistance sufficiently low, and its industrial merit is great.